1. Technical Field
The present invention relates generally to memory design evaluation circuits, and more particularly to a ring oscillator circuit for evaluating storage array performance via wordline-to-bitline output timing.
2. Description of the Related Art
Storage cell speed, circuit area and environmental operating ranges, e.g., supply voltage and temperature range, are critical limitations in today's processing systems and are predicted to become even more of a critical limitation as technologies move forward. In particular, static random access memory (SRAM) cells are used in processor caches and external storage to provide fast access to data and program instructions. Static storage cells are also used within processors and other digital circuits for storing values internally, for example, in processor registers.
With processor cycle frequencies reaching well above 4 Ghz, development of SRAM cells that can store and provide access to stored values within that period has become necessary. However, actually measuring the internal wordline-to-bitline timing and in particular the bitline evaluation time of memory cells presents a challenge. In a typical storage cell, there is no mechanism for determining bitline timing margin, except for evaluation performed by timing the read access of the cells after writing different patterns and decreasing the read cycle timing until failure occurs. If a probe is used to attempt to measure the internal timing of a read operation, the probe alters the timing of the cell, yielding incorrect results.
Memory cell transition times involving bitline and wordline read operations, sometimes in combination with write operations, have been evaluated using ring oscillator circuits or cascaded cell delay circuits wherein a large number of cells are cascaded. A ring oscillator may be formed with feedback of an output of the last cell to an input of the first cell, or a one-shot delay may be measured through the cascade of cells. The frequency at which the ring oscillator operates or the one-shot delay indicates the transition time performance, which provides some measure of ultimate operating frequency and access times. Typically, the cell design is then changed in subsequent design iterations having parameters adjusted in response to the results of the ring oscillator test.
However, present ring oscillator circuits and other delay-oriented circuits for performing delay tests typically either are not applied on production dies and/or do not test the actual storage cells under actual bitline loading conditions identical to placement and number of the cells within an array. Further, read cycle measurements are not measured independently, since the inclusion of a cell in the oscillator ring or delay line requires that the cell value will be written in some manner to provide a change in the bitline that is propagated from the previous cell.
It is therefore desirable to provide a test circuit and method for accurately measuring bitline timing under the complete column loading conditions of an actual array. It would further be desirable to measure the wordline-to-bitline access timing under actual loading conditions. It is further desirable to provide such a test circuit that can be integrated within a production storage device.